View ADUC831BS_459237.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
PRELIMINARY TECHNICAL DATA
MicroConverter (R), 12- Bit ADC with Embedded 62KB FLASH MCU
Preliminary Technical Data
ADuC831
A D C0 A D C1 . . .
MU X
T/H
ADuC831
12-BIT D AC
BU F
D AC
FEATURES ANALOG I/O 8-Channel, High Accuracy 12-Bit ADC High Speed 200 kSPS On-Chip, 100 ppm/ oC Voltage Reference DMA Controller for High-Speed ADC-to-RAM capture Two 12-Bit Voltage Output DACs Dual Output PWM/SD DACs On-Chip Temperature Sensor Function Memory 62Kbytes On-Chip Flash/EE Program Memory 4KBytes On-Chip Flash/EE Data Memory Flash/EE, 100 Yr Retention, 100 Kcycles Endurance 2304 Bytes On-Chip Data RAM 8051 Based Core 8051-Compatible Instruction Set (16 MHz Max) 12 MHz Nominal Operation (16MHz Max) 12 Interrupt Sources, Two Priority Levels Dual Data Pointer Extended 11-bit Stack Pointer On-Chip Peripherals Time Interval Counter (TIC) UART and SPI (R) Serial I/O Watchdog Timer (WDT), Power Supply Monitor (PSM) Power Specified for 3 V and 5 V Operation Normal Idle and Power-down Modes APPLICATIONS Intelligent Sensors (IEEE1451.2-Compatible) Battery Powered Systems (Portable PCs, Instrument Monitors) Transient Capture Systems DAS and Communications Systems Control Loop Monitors(Optical Networks/Basestations) Pin Compatible Upgrade to existing ADuC812 systems which require additional code or data memory. Runs from 1-16MHz external crystal. Also available ADuC832, Upgrade to ADuC812 systems. Runs from 32KHz external crystal with on-chip PLL.
12-BIT D AC
12 -B IT A D C
BU F
D AC
16-BIT DAC
H AR D WAR E C ALIBR A TION
A D C5 A D C6 A D C7
16-BIT DAC
P WM 0
MU X
PW M1
16-BIT PW M
16-BIT PWM
TEM P S EN SO R
80 5 1-B AS ED MC U WITH AD D ITION AL PE RIP H ER AL S
6 2 K BY TES FL A SH /EE PR OGR AM M EMO RY 4 KB YTES FLA SH /E E DA TA MEM OR Y 2 304 BY TE S US ER R AM
3 x 16 B IT TIM ER S 1 x R E AL TIM E C L OC K
IN TER N AL B AN D GAP V R EF
OSC
POW ER S UP PLY M ON WA TC H DO G TIME R
SP I A N D U A RT SE RIA L I/O, HIGH C U R RE N T P IN S
4 x P AR A L LE L P OR TS
V R EF
X TAL 1
XT AL 2
GENERAL DESCRIPTION
The ADuC831 is a complete smart transducer front-end, integrating a high-performance self calibrating multichannel ADC, dual DAC and programmable 8-bit MCU on a single chip. The microcontroller core is an 8052 and therefore 8051-instruction-set-compatible with 12 core clock periods per machine cycle. 62 Kbytes of nonvolatile Flash/EE program memory are provided on-chip. 4 Kbytes of nonvolatile Flash/EE data memory, 256 bytes RAM and 2 KBytes of extended RAM are also integrated on-chip. The ADuC831 also incorporates additional analog functionality with two 12-bit DACs, power supply monitor, and a bandgap reference. On-chip digital peripherals include two 16-bit DACs, dual output 16-bit PWM, watchdog timer, time interval counter, three timers/counters, Timer 3 for Baud Rate generation and two serial I/O ports (SPI and UART) On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. A functional block diagram of the ADuC831 is shown above with a more detailed block diagram shown in figure 1 (page 6). The part is specified for 3 Vand 5V operation over the industrial temperature range and is available in a 52-lead, plastic quad flatpack package and in a 56-lead, chip scale package.
MicroConverter is a registered trademark of Analog Devices, Inc. SPI is a registered trademark of Motorola Inc.
REV. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
-1-
PRELIMINARY TECHNICAL DATA
DD = DVDD = 3.0 V or 5.0 V 610%, REFIN/REFOUT = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz, fSAMPLE = 200 kHz, DAC VOUT Load to AGND; RL = 2 kV, CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.)
SPECIFICATIONS
Parameter ADC CHANNEL SPECIFICATIONS DC ACCURACY3, 4 Resolution Integral Nonlinearity
1, 2 (AV
ADuC831
ADUC831BS VDD = 5 V VDD = 3 V
Unit
Test Conditions/Comments
Differential Nonlinearity CALIBRATED ENDPOINT ERRORS5, 6 Offset Error Offset Error Match Gain Error Gain Error Match USER SYSTEM CALIBRATION7 Offset Calibration Range Gain Calibration Range DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)8 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance9 TEMPERATURE SENSOR10 Voltage Output at 25C Voltage TC Acquisition Time Required DAC CHANNEL SPECIFICATIONS DC ACCURACY11 Resolution Relative Accuracy Differential Nonlinearity Offset Error Full-Scale Error Full-Scale Mismatch ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Resistive Load Capacitive Load Output Impedance ISINK
12 1/2 1.5 1.5 1
12 1/2 1.5 1.5 1
Bits LSB typ LSB max LSB typ LSB typ
fSAMPLE = 100 kHz fSAMPLE = 100 kHz fSAMPLE = 200 kHz fSAMPLE = 100 kHz. Guaranteed No Missing Codes at 5 V
5 1 1 6 1 1.5 5 2.5
5 1 1 6 1 1.5 5 2.5
LSB max LSB typ LSB typ LSB max LSB typ LSB typ % of VREF typ % of VREF typ fIN = 10 kHz Sine Wave fSAMPLE = 100 kHz
70 -78 -78 0 to VREF 1 0.1 20 600 -3.0 1
70 -78 -78 0 to VREF 1 0.1 20 600 -3.0 1
dB typ dB typ dB typ Volts A max A typ pF max mV typ mV/C typ uS typ Can vary significantly (> 20%) from device to device
12 3 0.5 60 15 30 10 0.5 0 to VREF 0 to VDD 10 100 0.5 50
12 3 1 60 15 30 10 0.5 0 to VREF 0 to VDD 10 100 0.5 50
Bits LSB typ LSB typ mV max mV typ mV max mV typ % typ V typ V typ k typ pF typ typ A typ
Guaranteed 12-Bit Monotonic
% of Full-Scale on DAC1
REV. PrD
-2-
ADuC831-SPECIFICATIONS1,2 (continued)
Parameter DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy REFERENCE INPUT/OUTPUT REFIN Input Voltage Range9 Input Impedance REFOUT Output Voltage REFOUT Tempco FLASH/EE MEMORY PERFORMANCE CHARACTERISTICS12, 13 Endurance Data Retention WATCHDOG TIMER CHARACTERISTICS Oscillator Frequency TIME INTERVAL COUNTER Oscillator Frequency POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range AVDD Power Supply Trip Point Accuracy DVDD Trip Point Selection Range DVDD Power Supply Trip Point Accuracy DIGITAL INPUTS Input High Voltage (VINH) XTAL1 Input High Voltage (VINH) Only Input Low Voltage (VINL) Input Leakage Current (Port 0, EA) Logic 1 Input Current (All Digital Inputs) 15 10 2.3/VDD 150 2.5 2.5% 2.5 100 15 10
PRELIMINARY TECHNICAL DATA
ADUC831BS VDD = 5 V VDD = 3 V
Unit s typ nV sec typ V min/max k typ V min/max V typ ppm/C typ
Test Conditions/Comments Full-Scale Settling Time to Within 1/2 LSB of Final Value 1 LSB Change at Major Carry
2.3/VDD 150 2.5 2.5% 2.5 100
Initial Tolerance @ 25C
100,000 100
100,000 100
Cycles min Years min
32 32 2.63 4.63
32 32
kHz typ kHz typ Vmin Vmax
10% Accurate 10% Accurate Four Trip Points Selectable in This Range Programmed via TPA 1-0 IN PSMCON
3.5 2.63 4.63
% max Vmin Vmax Four Trip Points Selectable in This Range Programmed via TPD1-0 in PSMCON
3.5 2.4 4 0.8 10 1
% max V min V min V max A max A typ A max A typ A max A typ A max A typ pF typ
1
VIN = 0 V or VDD VIN = 0 V or VDD VIN = VDD VIN = VDD VIL = 450 mV VIL = 2 V VIL = 2 V
10 1 Logic 0 Input Current (Port 1, 2, 3) -80 -40 Logic 1-0 Transition Current (Port 1, 2, 3) -700 -400 Input Capacitance 10
1 -40 -400 10
-3-
REV.PrD
PRELIMINARY TECHNICAL DATA
ADuC831
Parameter DIGITAL OUTPUTS Output High Voltage (VOH) ADUC831BS VDD = 5 V VDD = 3 V 2.4 4.0 Output Low Voltage (VOL) ALE, PSEN, Ports 0 and 2 Port 3 Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS14, 15, 16 IDD Normal Mode17 2.6 Unit V min V typ Test Conditions/Comments VDD = 4.5 V to 5.5 V ISOURCE = 80 A VDD = 2.7 V to 3.3 V ISOURCE = 20 A ISINK = 1.6 mA ISINK = 1.6 mA ISINK = 8 mA ISINK = 8 mA
0.4 0.2 0.4 0.2 10 5 10 43 32 26 8 25 18 15 7 50 5
0.2 0.2 5 10
V max V typ V max V typ A max A typ pF typ mA max mA typ mA typ mA typ mA max mA typ mA typ mA typ A max A typ
16 12 3 17 6 2 50 5
IDD Idle Mode
MCLKIN = 16 MHz MCLKIN = 16 MHz MCLKIN = 12 MHz MCLKIN = 1 MHz MCLKIN = 16 MHz MCLKIN = 16 MHz MCLKIN = 12 MHz MCLKIN = 1 MHz
IDD Power-Down Mode18
NOTES 1 Specifications apply after calibration. 2 Temperature range -40C to +85C. 3 Linearity is guaranteed during normal MicroConverter Core operation. 4 Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity. 5 Measured in production at VDD = 5 V after Software Calibration Routine at 25C only. 6 User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent. 7 The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC831 can compensate. 8 SNR calculation includes distortion and noise components. 9 Specification is not production tested, but is supported by characterization data at initial product release. 10 The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result. 11 DAC linearity is calculated using: reduced code range of 48 to 4095, 0 to VREF range reduced code range of 48 to 3995, 0 to VDD range DAC output load = 10 k and 50 pF. 12 Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance). 13 Endurance Cycling is evaluated under the following conditions: Mode = Byte Programming, Page Erase Cycling Cycle Pattern = 00Hex to FFHex Erase Time = 20 ms Program Time = 100 s 14 IDD at other MCLKIN frequencies is typically given by: Normal Mode (VDD = 5 V): IDD = (1.6 nAs x MCLKIN) + 6 mA Normal Mode (VDD = 3 V): IDD = (0.8 nAs x MCLKIN) + 3 mA Idle Mode (VDD = 5 V): IDD = (0.75 nAs x MCLKIN) + 6 mA Idle Mode (VDD = 3 V): IDD = (0.25 nAs x MCLKIN) + 3 mA Where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA. 15 IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation. 16 IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles. 17 Analog IDD = 2 mA (typ) in normal operation (internal VREF, ADC and DAC peripherals powered on). 18 EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement. Typical specifications are not production tested, but are supported by characterization data at initial product release. Specifications subject to change without notice. Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information.
REV. PrD
-4-
PRELIMINARY TECHNICAL DATA
ADuC831
ABSOLUTEMAXIMUMRATINGS*
(TA = 25C unless otherwise noted)
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V DVDD to DGND, AVDD to AGND . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to DGND . . . . . -0.3 V, DVDD + 0.3 V Digital Output Voltage to DGND . . . . -0.3 V, DVDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . -0.3 V, AVDD + 0.3 V Analog Inputs to AGND . . . . . . . . . . . -0.3 V, AVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model ADUC831BS ADuC831BCP
Temperature Range -40C to +85C -40C to +85C
Package Description 52-Lead Plastic Quad Flatpack 56-Lead Chip Scale Package
Package Option S-52 CP-56
PIN CONFIGURATION
' $ 3
' $ 3
' $ 3
' $ 3
9 '
' '
' 1 * '
' $ 3
' $ 3
' $ 3
' $ 3
7
( / $
1 ( 6 3
$ (
& ' $ 3

3$'&7 3$'&7(; 3$'& 3$'&
' $ 3
' $ 3
' $ 3
' $ 3
G G 9 '
G Q * '
' $ 3
' $ 3
' $ 3
' $ 3
( / $
1 ( 6 3
$ (

3,1 ,'(17,),(5

33:0$$ 33:0$$ 3$$ 3$$ '*1' '9'' ;7$/ ;7$/ 3$$ 3$$ 3$$ 3$$ '026,

3$'&7(; S$'& 3$'& $9'' $9'' $*1' $*1' $*1' &UHI 9UHI '$& '$& 3$'& 3$'&66

3$$ 3$$ 3$$ 3$$ '*1' '*1' '9'' ;7$/ ;7$/ 3$$ 3$$ 3$$ 3$$ 026,'
3,1 ,'(17,),(5

$9'' $*1' &5() 95() '$& '$& 3$'& 3$'&66 3$'&

$'X&
723 9,(: 1RW WR 6FDOH

$'X& 3,1 &63
723 9,(: 1RW WR 6FDOH

& ' $ 3 7 ( 6 ( 5 ' [ 5 3 ' [ 7 3 7 1 , 3 0 9 :' 3 2 6 , 0 7 1 , 3
' '
' 1 * '
0
7 6 9 : 1 3 2 && 0 :7 3 73 3
5 : 3
' 5 3
' ?
. & 2 / & 6
& ' $ 3
& ' $ 3
7 ( 6 ( 5
' ; 5 3
' ; 7 3
2 6 , 0 2 7 1 , 3
7 1 , 3
G G 9 '
G Q * '
7
3
7
5 : 3
3
' 5 3
'
. & 2 / & 6
-5-
REV. PrD
PRELIMINARY TECHNICAL DATA
ADuC831
ADuC831
$'& $'&
0X[
12-BIT VOLTAGE OUTPUT DAC
DAC CONTROL
DAC0
7+
%LW $'&
ADC CONTROL AND CALIBRATION
12-BIT VOLTAGE OUTPUT DAC
16-BIT DAC
DAC1
$'&
$'&
PWM CONTROL
4% DAC
16-BIT PW M
16-BIT PW M
16-BIT
PWM0
MUX
PWM1
TEMP SENSOR
62 KBYTES PROGRAM FLASH/EE INCLUDING USER DOWNLOAD MODE 4 KBYTES DATA FLASH/EE
256 Bytes USER RAM
T0
BANDGAP REFERENCE
95()
8052
MCU CORE
2 KBytes USER XRAM
%8)
WATCHDOG TIMER
16-BIT COUNTER TIMERS
T1
T2 T2EX
2 X DATA POINTERS 11-BIT STACK POINTER
DOWNLOADER DEBUGGER
SINGLE-PIN EMULATOR
POWER SUPPLY MONITOR
,17
&5()
TIME INTERVAL COUNTER (WAKEUP CCT)
,17
325
ASYNCHRONOUS SERIAL PORT (UART)
UART TIMER
SYNCHRONOUS SERIAL INTERFACE (SPI )
OSC
RESET
1$ (( 6 3
XTAL1
DGND
DGND
DGND
AGND
RXD
TXD
MISO
Figure 1 ADuC831 Block Diagram (Shaded areas are features not present on the ADuC812)
REV. PrD
-6-
XTAL2
DVDD
DVDD
DVDD
AVDD
MOSI
6 6
ALE
PRELIMINARY TECHNICAL DATA
ADuC831
PIN FUNCTION DESCRIPTIONS
Mnemonic DVDD AVDD CREF VREF
Type Function P P I I/O Digital Positive Supply Voltage, 3 V or 5 V Nominal Analog Positive Supply Voltage, 3 V or 5 V Nominal Decoupling Input for On-Chip Reference. Connect 0.1 F between this pin and AGND. Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference. Analog Ground. Ground Reference point for the analog circuitry. Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure any of these Port Pins as a digital input, write a "0" to the port bit. Port 1 pins are multifunction and share the following functionality. Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR. Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to a 1 to 0 transition of the T2 input. Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for Counter 2. Slave Select Input for the SPI Interface Digital Output Pin Digital Output Pin Serial Clock Pin for Serial Interface Clock SPI Master Output/Slave Input Data I/O Pin for SPI Interface SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface Voltage Output from DAC0 Voltage Output from DAC1 Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device. Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also contain various secondary functions which are described below. PWM Clock Input PMW0 Voltage Output. PWM outputs can be configured to uses ports 2.6 & 2.7 or 3.3 and 3.4 PMW1 Voltage Ouput. See CFG831 Register for further Information. Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. Timer/Counter 0 Input Timer/Counter 1 Input Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion. Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory. Read Control Signal, Logic Output. Enables the external data memory to Port 0. Output of the Inverting Oscillator Amplifier Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Digital Ground. Ground reference point for the digital circuitry. Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space. -7- REV. PrD
AGND P1.0-P1.7
G I
ADC0-ADC7 T2 T2EX SS D1 D0 SCLOCK MOSI MISO DAC0 DAC1 RESET P3.0-P3.7
I I I I O O I/O I/O I/O O O I I/O
PWMC PWM0 PWM1 RxD TxD INT0 INT1 T0 T1 CONVST WR RD XTAL2 XTAL1 DGND P2.0-P2.7 (A8-A15) (A16-A23)
I O O I/O O I I I I I O O O I G I/O
PRELIMINARY TECHNICAL DATA
ADuC831
PIN FUNCTION DESCRIPTION (continued)
Mnemonic PSEN
Type Function O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET. Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch all instructions from external program memory. Port 0 is an 8-Bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s.
ALE
O
EA
I
P0.7-P0.0 (A0-A7)
I/O
TERMINOLOGY
ADC SPECIFICATIONS Integral Nonlinearity
This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition.
Differential Nonlinearity
The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise +distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS Relative Accuracy
This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.
Gain Error
This is the deviation of the last code transition from the ideal AIN voltage (Full Scale - 1.5 LSB) after the offset error has been adjusted out.
Signal to (Noise + Distortion) Ratio
Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error.
Voltage Output Settling Time
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc.
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV sec.
Full-Scale Error
This is the deviation of the full scale output voltage from the ideal.
REV. PrD
-8-

▲Up To Search▲

Price & Availability of ADUC831BS

	To Download ADUC831BS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .